1) Field of the Invention
This invention relates generally to devices and the fabrication of semiconductor devices and more particularly to the fabrication of a vertical PNP transistors and methods for making same in BiCMOS processes.
2) Description of the Prior Art
High speed and low-power LSIs, which operate in the GHz band, has been required for many applications such as the mobile telecommunication and wireless LNAs. The SiGe BiCMOS LSIs have been widely studied as potential candidate. However, the performance of conventional BiCMOS gate circuit, which is composite by CMOS buffer and NPN output driver is poor when the power supply is lower. This degradation at low power supply is due to the Vbe voltage loss and substrate bias effect of the CMOSFET (FIG. 15A). To overcome this problem, several BiCMOS circuits have been proposed. Adding high-speed PNP transistors into the SiGe BiCMOS to form so-called complementary BiCMOS (CBiCMOS) can eliminate voltage loss (See FIG. 15B). The CBiCMOS circuit makes BiCMOS technology application in deep sub-micron regime.
FIG. 15A shows a schematic of a principle circuit of BiCMOS gate and output voltage swing for a conventional BiCMOS. FIG. 15B shows a schematic of a. principle circuit of BiCMOS gate and output voltage swing for a base-charge CBiCMOS. The output voltage is shifted to Vcc+2Vbe, No voltage loss occur.
There is a need for an improved structure and process for a SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The more relevant technical developments in the literature can be gleaned by considering the following.
US 20040099895 A1—Gray, Peter B.; et al.—includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow.
U.S. Pat. No. 6,699,765—Shideler, et al.—Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer. A transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer.
U.S. Pat. No. 5,930,635—Bashir, et al.—Complementary Si/SiGe heterojunction bipolar technology—The method results in the fabrication of vertical NPN and PNP transistors which have an identical structure and mode of operation.
U.S. Pat. No. 6,630,377—Panday, et al.—Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process.
U.S. Pat. No. 6,359,317—Carroll, et al.—shows a Vertical PNP bipolar transistor and its method of fabrication.
U.S. Pat. No. 5,943,564—Chen, et al., BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures
D. L. Harame et al., “Current status and future trends of SiGe BiCMOS Technology”, IEEE Trans. Electron Devices, vol. 48., pp. 2575-2593, November 2001.
T. Nagano, S. Shukuri, M. Hiraki, M. Minami, A. Watanable and T. Nishida, “What Can Replace BiCMOS at Low supply Voltage Regime?”, IEDM Tech. Dig., p. 393, 1992
C. T. Chuang and D. D. Tang, “High-Speed Low Power AC-Coupled Complementary Push-Pull ECL Circuit,” IEEE J. Solid-State Circuit, Vol. 27, No. 4, p. 660, 1992.
T. Ikeda, T. Nakashima, S. Kobo, H. Jouba and M. Yamawaki, “A High Performance CBiCMOS with Novel Self-Aligned Vertical PNP Transistor,” Proc. of 1994 Bipolar/BiCMOS Circuits & Technology Meeting, p. 238, 1994.